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| October 2003 rev 1.0 Features Generates an EMI optimized clocking signal at output. Input frequency - 14.31818 MHz. Frequency outputs: o o 120 MHz (modulated) - default. 72 MHz (modulated) or 48 (modulated) selectable via I2C MHz ASM3P2508A ASM3P2508A modulates the output of PLL in order to spread the bandwidth of a synthesized clock, thereby decreasing the peak amplitudes of its harmonics. This results in significantly lower system EMI compared to the typical narrow band signal produced by oscillators and most clock generators. Lowering EMI by increasing a signal's bandwidth is called spread spectrum clock generation. The ASM3P2508A has a feature to power down the 72MHz / 48MHz output by writing data into specific registers in the device via I2C. By writing a `0' into bit 1 of byte 0, the PLL block generating 72 MHz / 48MHz can be powered down. Writing `0' into bit `7' of byte 1 selects an output of 72 MHz on FOUT2CLK while a `1' at the same location selects a 48 MHz clock output. However, the I2C block, crystal oscillator, and the PLL block generating 120MHz would be always running. 1% Centre spread. Modulation rate: 40 KHz. Byte Write via I2C Supply voltage range 3.3V ( 0.3V). Available in 8-pin SOIC package. Commercial and Industrial Temperature range. Product Description The ASM3P2508A is a versatile spread spectrum frequency modulator. The ASM3P2508A reduces electromagnetic interference (EMI) at the clock source. The ASM3P2508A allows significant system cost savings by reducing the number of circuit board layers and shielding that are required to pass EMI regulations. The Block Diagram VDD XIN XOUT Crystal Oscillator PLL 1 FOUT1CLK (120 MHz) SCL SDA I2C Interface PLL 2 FOUT2CLK (72 MHz / 48 MHz) VSS Alliance Semiconductor 2575 Augustine Drive * Santa Clara CA * Tel: 408-855-4900 * Fax: 408-855-4999 * www.alsc.com October 2003 rev 1.0 Pin Configuration XIN XOUT VDD FOUT1CLK 1 2 8 7 ASM3P2508A VSS SCL SDA FOUT2CLK ASM3P2508A 3 4 6 5 Pin Description Pin Name XIN XOUT VDD FOUT1CLK FOUT2CLK SDA SCL VSS Type I O P O O I/O I P Description Connection to crystal Connection to crystal Power supply for the analog and digital blocks Clock output-1 (120 MHz) - default Clock output-2 ( 72 MHz / 48 MHz) I2C Data I2C Clock Ground to entire chip Peak Reducing EMI Solution 2 of 13 October 2003 rev 1.0 Absolute Maximum Ratings ASM3P2508A Parameter Rating Unit Supply voltage, DC (VSS - 0.5) to 7 V Input voltage, DC (VSS-0.5) to (VDD+0.5) V Output voltage, DC (VSS-0.5) to (VDD + 0.5) V Input clamp current (VI<0 or VI>VDD) -50 to +50 mA Output clamp current (VI<0 or VI>VDD) -50 to +50 mA Storage temperature -65 to +125 C Ambient temperature range, under bias -55 to 125 C Junction temperature 150 C Lead temperature (soldering 10 sec) 260 C Input static discharge voltage protection 2 kV (MIL -STD 883E, Method 3015.7) Note: These are stress ratings only and functional operation is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. Symbol VDD VI VO IIK IOK TS TA TJ Operating Conditions Parameter Supply Voltage Ambient Operating Temperature Range Crystal Resonator Frequency Output Driver Load Capacitance Symbol VDD TA FXIN CL Condition / Description 3.3V 10% Min 3 -10 14.31818 15 Typ 3.3 Max 3.6 +70 Unit V C MHz pF Peak Reducing EMI Solution 3 of 13 October 2003 rev 1.0 DC Electrical Characteristics Parameter Symbol Conditions / Description Overall VDD=3.3V, FCLK=14.31818MHz, Supply Current, IDD Dynamic CL=15pF VDD = 3.3V, Software Power Supply Current, IDDL Static Down All input pins High-Level Input VIH VDD=3.3V Voltage Low-Level Input VDD=3.3V VIL Voltage High-Level Input IIH Current Low-Level Input IIL Current (pull-up) High-Level Output VDD=V(XIN) = 3.3V, VO=0V IxOH Source Current Low-Level Output VDD=3.3V, V(XIN)=VO=5.5V IxOL Source Current Clock Outputs (FOUT1CLK, FOUT2CLK) High-Level Output VO=2.4V IOH Source Current Low-Level Output IOL VO=0.4V Sink Current Output Impedance VO=0.5VDD; output driving high ZOH ZOL Vo=0.5VDD; output driving low Min Typ 43 tbd 2.0 VSS-0.3 -1 -20 10 -10 -36 21 -21 -20 23 29 27 ASM3P2508A Max Unit mA mA VDD+0.3 0.8 1 -80 30 -30 V V A A mA mA mA mA Peak Reducing EMI Solution 4 of 13 October 2003 rev 1.0 AC Electrical Characteristics Conditions/ Description VO = 0.3V to 3.0V; CL = Rise Time tr 15pF VO = 3.0V to 0.3V; CL = Fall Time tf 15pF Ratio of pulse width (as Clock Duty measured from rising edge to next falling edge at 2.5V) Cycle to one clock period On rising edges 500 uS apart at 2.5 V relative to an Jitter, Long ideal clock, PLL B inactive * Tj (LT) Term On rising edges 500 uS apart at 2.5 V relative to an ideal clock, PLL B active * From rising edge to next rising edge at 2.5 V, PLL B inactive * Jitter, peak to Tj (T) peak From rising edge to next rising edge at 2.5 V, PLL B active * Clock Output active from power up, tSTB Stabilization RUN Mode via Software Time Power Down * CL = 15 pF, Fxin = 14.31818 MHz, Fout = 50 MHz Parameter Symbol Min Typ 2.1 1.9 45 55 Max Unit ns ns % ASM3P2508A 45 165 110 390 125 pS pS us Crystal Specifications Fundamental AT cut parallel resonant crystal Nominal Frequency Frequency Tolerance Operating temperature range Storage Temperature Load Capacitance Shunt capacitance ESR 14.31818 MHz +/- 50 ppm or better at 25C -20C to +85C -40C to +85C 18pF 7 pF maximum 25 Peak Reducing EMI Solution 5 of 13 October 2003 rev 1.0 General I2C Serial Interface Information The information in this section assumes familiarity with I2C programming. How to Write through I2C: * * * * * * * * * * Master (host) sends a start bit. Master (host) sends the write address XX (H) ASM3P2508A device will acknowledge Master (host) sends the beginning byte location (=N) ASM3P2508A device will acknowledge Master (host) sends a dummy byte count ASM3P2508A device will acknowledge Master (host) starts sending byte N through byte N+X - 1* ASM3P2508A device will acknowledge each byte one at a time. Master (host) sends a Stop bit Controller (Host) Start Bit Slave Address XX(H) ACK Beginning byte location (=N) ACK Dummy byte count ACK Beginning byte (Byte N) ACK Next Byte (Byte N+1) ACK ---------Last Byte (Bye N+X-1) ACK Stop Bit ------Not Acknowledge Stop Bit ACK ASM3P2508A (slave/receiver) ASM3P2508A How to Read through I2C: * * * * * * * * * * * * * Master (host) will send start bit. Master (host) sends the write address XX (H) ASM3P2508A device will acknowledge Master (host) sends the beginning byte location (=N) ASM3P2508A device will acknowledge Master (host) will send a separate start bit Master (host) sends the read address XX (H) ASM3P2508A device will acknowledge ASM3P2508A device will send the dummy byte count Master (host) acknowledges ASM3P2508A device sends byte N through byte N+X - 1* Master (host) will need to acknowledge each byte Master (host) will send a stop bit (* X is the number of bytes) Controller (Host) Start Bit Slave Address XX(H) ACK Beginning Byte = N ACK Repeat start Slave address ACK Dummy Byte Count Beginning byte N ACK Next Byte N+1 ACK ---Last Byte (Byte N+X-1) ASM3P2508A (slave/receiver) Peak Reducing EMI Solution 6 of 13 October 2003 rev 1.0 Software A demonstration board and software is available for the ASM3P2508A. The software can operate under Windows 95 and Windows NT. The opening screen of the software is shown in figure 2. ASM3P2508A By pressing the drop down arrow of Port ID toolbar button, any of the three parallel ports ( LPT1 LPT2 or LPT3 ) can be selected. The selected parallel port is used for the I2C data transfer. Opening Screen Peak Reducing EMI Solution 7 of 13 October 2003 rev 1.0 Programming the PLLs: Select the CGEN check box to enable the PLL and the EMI reduction check box to enable the spread spectrum on. Enter the input frequency (in Mhz), output frequency (Mhz) , percentage error and modulation rate (Khz) in the respective input boxes. To enable the OUT1 OUT2 and REFOUT click the respective check box. To tristate all the outputs click the tristate check box. Select the type of the modulation between the center or down and enter the deviation (percentage) in the respective input box. Profile type can be selected between the sine triangular or lexmark. EMI reduction enable/disable available for the PLL1. option is only ASM3P2508A error box. 4. Enter the modulation rate say 30 khz in the modulation rate box. 5. Select the second output frequency by pressing the pull down menu of the out2 frequency. The value of OUT2 frequency can be selected as vco/2, vco/3, vco/4, vco/5, vco/6, vco/8, vco/9, vco/10, vco/12, vco/15, vco/18, vco/24 or vco/30. 6. Select the type of the deviation, percentage deviation and type of the profile. 7. Enter the data for PLL2 in a similar manner. Writing the data to the chip: There are two different ways of writing data to the chip. 1. Writing through the file. 2. Enter the required data in the respective forms and calculate and then write. For Example: 8. Press the CalcResult button to load the data in the ROM data panel. 9. To write this data to the chip press the I2CWrite button. 1. Enter the input freq say 15 Mhz, in the input frequency box. 2. Enter the required output frequency say 65 Mhz, in the out1 frequency box. 3. Enter the percentage error say 0.01 in the Peak Reducing EMI Solution 8 of 13 October 2003 rev 1.0 Results Window ASM3P2508A An example of a Byte Write via I2C to partially `power down' the device: ASM3P2508A can be partially `powered down' using bit 1 of Byte 0. The organization of the register bits for Byte `0' is given with default values below: Bit7 Resv. 0 Bit6 Resv. 1 Bit5 Resv. 0 Bit4 Resv. 1 Bit3 Resv. 0 Bit2 Resv. 1 Bit1 PLL2 Enable 1 Bit0 PLL1 Enable 1 Reading the data from the Chip 1. To read the data from the chip through I2C, press the I2CRead button. 2. The data can be seen in the ROM data field. 3. This data which is read from the chip can be saved in the file by clicking the Save button. The function of partial power down of the device is of interest to us - that is bit 1 of Byte 0. In the default mode this bit is logic `1'. As such, the Byte 0 default value is 57 (H). To put ASM3P 2508A in `power down' mode, the bit 0 of byte 0 is to be changed to logic `0'. Hence writing a 55 (H) via i2C into byte 0 would put the device in partial `power down' mode where the PLL block generating 72 MHz / 48 MHz would be powered down while I2C block, crystal oscillator, and the PLL block generating 120 MHz would still be active. The organization of the register bits is as below: Bit7 Resv. 0 Bit6 Resv. 1 Bit5 Resv. 0 Bit4 Resv. 1 Bit3 Resv. 0 Bit2 Resv. 1 Bit1 PLL2 Enable 0 Bit0 PLL1 Enable 1 Peak Reducing EMI Solution 9 of 13 October 2003 rev 1.0 Package Information ASM3P2508A 8-Pin SOIC Symbol A A1 B C D E H e L Dimensions in inches Min 0.053 0.004 0.013 0.007 0.188 0.150 0.228 0.050 BSC 0.016 0 0.035 8 Max 0.069 0.010 0.022 0.012 0.197 0.158 0.244 Dimensions in millimeters Min 1.35 0.10 0.33 0.18 4.78 3.80 5.80 1.27 BSC 0.40 0 0.89 8 Max 1.75 0.25 0.53 0.27 5.00 4.01 6.20 Peak Reducing EMI Solution 10 of 13 October 2003 rev 1.0 Ordering Codes Part number ASM3P2508A-08-ST ASM3P2508A-08-SR ASM3I2508A-08-ST ASM3I2508A-08-SR Package Configuration 8-PIN SOIC 8-PIN SOIC 8-PIN SOIC 8-PIN SOIC ASM3P2508A TUBE TAPE AND REEL TUBE TAPE AND REEL Peak Reducing EMI Solution 11 of 13 October 2003 rev 1.0 ASM3P2508A Alliance Semiconductor Corporation 2595, Augustine Drive, Santa Clara, CA 95054 Tel# 408-855-4900 Fax: 408-855-4999 www.alsc.com Copyright (c) Alliance Semiconductor All Rights Reserved Preliminary Information Part Number: ASM3P2508A Document Version: v1.0 (c) Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. Peak Reducing EMI Solution 12 of 13 October 2003 rev 1.0 ASM3P2508A Peak Reducing EMI Solution 13 of 13 |
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